parasitic parameter
英 [ˌpærəˈsɪtɪk pəˈræmɪtə(r)]
美 [ˌpærəˈsɪtɪk pəˈræmɪtər]
网络 寄生参数
双语例句
- A Investigation of on Chip Parasitic Parameter Extration; Three-dimensional Massively Parallel Numerical Simulation of Kerosene-fueled Scramjet
超大规模集成电路寄生参数提取研究煤油超燃冲压发动机三维大规模并行数值模拟 - Because of the influence of some parasitic parameter in PIN diode and circuits, some measure must be taken to compensate the circuits.
由于PIN管和开关电路中存在一些寄生参量的影响，实际制作中可采取相应措施对电路进行补偿。 - The traditional methods of parasitic parameter extraction in EDA, which based on the concept of lumped component, have lost their accuracy.
传统的EDA设计中的基于集总电路概念的参数提取算法已经失去准确性。 - Non-parasitic Parameter Carrier in Mixed Integrated Circuit
混合集成电路用无寄生参数载体 - Application of wavelet analysis in parasitic parameter extraction
小波分析在寄生参数提取中的应用 - This paper states design of layout and examination of DRC ( Design Rule Checking) and LVS ( Layout Versus Schematic) and extract of RC parasitic parameter of a kind of memory of 16 digit.
阐述了对一种16位存储器版图设计中的DRC（DesignRuleChecking）即“设计规则检查”和LVS（LayoutVersusSchematic）即“版图和电路比较”、以及RC寄生参数的提取。 - A small expert system ( NNCE) is set up to calculate parasitic capacitance parameter of rectangle conductors which have been engraved by the so-called Nanoscope, based on BEM and neural network technique.
文中基于BEM和神经网络技术，通过定义等效长度概念，建立了一个计算寄生参数的小型专家系统NNCE，以实现对光刻后实际版图的寄生电容参数的有效提取。 - Extract of Parasitic Parameter of A Kind of Memory of 16 Digit
一种16位存储器版图的验证与参数提取 - Efficient preconditioning methods for 3-D parasitic parameter extraction using the boundary element method
三维边界元寄生参数提取中的有效预条件方法 - At last integrated EMI filter is realized and propose several ways to reduce the parasitic parameter.
在这基础上实现了EMI滤波器集成，并提出了几种减小寄生参数的方法。 - Novel techniques are proposed for modeling the distributed parasitic capacitance, parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.
提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及STACK内连线的不匹配的模型。 - In the deep submicron VLSI circuits, with the feature size scaled down and device density increased, parasitic parameter extraction has become one of the research focuses in the field of electronic design automation.
随着VLSI电路集成密度急剧增长及特征尺寸不断缩小，互连寄生参数提取已成为集成电路辅助设计中的一个研究热点.目前，三维互连寄生电容提取的研究得到广泛关注，并取得了很大进展。 - The parasitic parameter model of the modular power supply is built and the optimization strategies of improving the EMC performance are proposed.
建立了模块电源的寄生参数模型，提出改善模块电源EMC性能的措施。 - Including of RTL code logic synthesis, physical layout implementation, Design Rule Check, Layout with Schematic check, parasitic parameter extraction, Static Timing Analysis and format validation.
包括对RTL代码进行逻辑综合、物理版图实现、设计规则验证、版图与网表一致验证、寄生参数提取、静态时序分析和形式验证等。 - The parasitic parameters are extracted for building the parasitic parameter model of the FC-IPEM using an impedance analyzer. A method of paralleling external capacitor is proposed to improve measurement precision of structural capacitance.
采用阻抗分析仪测量半桥FC-IPEM的寄生参数，建立寄生参数模型，测量中，使用改进型寄生电容测量方法，提高了测量的准确性。 - And a high-frequency simulation modeling circuit is established with them. Using SABER software simulates the circuit, analysis the effects of passive circuit parasitic, the IGBT collector of heatsink parasitic capacitance parameter to common mode interference and differential interference.
使用Saber软件模拟仿真，对比分析了电路中的无源寄生参数、IGBT集电极对散热片的寄生电容等参数对差模干扰和共模干扰的影响。